1. Field of the Invention
The present invention relates to a display controller suitable for use, for example, in relatively small computer systems.
2. Description of the Related Art
Recently, inexpensive microprocessors, peripheral control large scale integrated circuits (LSIs), and memory LSIs have become available by virtue of remarkable advances in semiconductor technologies. Hence, a suitable combination of these components can be combined to form a relatively high performance computer system.
A display controller is a typical of peripheral LSI used in a computer system. The display system forms the nucleus of a man-machine interface and provides the interface between a microprocessor (CPU) and a display unit such as a cathode ray tube (CRT), a liquid crystal display (LCD), an electroluminescent display (ELD), or a plasma display panel (PDP). The display controller controls a video memory and its timing in accordance with the contents of a program.
A display controller adapted to switch the display unit from CRT to PDP or from PDP to CRT for image display and a data processing system with such a display controller are described in U.S. patent application Ser. Nos. 207,790; 207,986; 208,044; and 208,130; filed on Jun. 17, 1988, on behalf of inventor Hideki Zenda and assigned to the same assignee as the present invention. The arrangements and operations of the display controller and the data processing system described in the applications are incorporated herein by reference.
When the display unit is switched from CRT to PDP or from PDP to CRT by the display controller as described in the above-noted applications, an NMI interruption signal is generated and communicated to the microprocessor. The CPU executes the basic input/output system (BIOS) in response to the NMI interruption signal and, thus, display parameters for the CRT or PDP are set in an I/O register (see the U.S. patent application Ser. No. 208,130).
Such a transfer scheme for display parameters involves the execution of the BIOS, which increases the burden imposed on firmware. In addition, such a scheme is generally incompatible with systems that do not make use of an NMI interruption signal.